Build a full SoC at RTL with the best trade-off
(Time to Market, Power, Performance, Area, IP Reuse, Engineering cost)
Thanks to its build and signoff capabilities and its unified database, STAR helps during the design process of complex SoCs to:
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SoC design groups continue facing high pressure to innovate quickly and consistently deliver.
In current design flows, RTL design is where most of the innovation is expected since it provides flexibility with a highest reusability potential.
To deliver greater functionality, higher performance, at much lower power for next-generation applications such as for automotive, mobile, and servers, leading edge SoCs are needed. Meeting time-to-market requirements and lowering the overall cost including design steps also become a critical factor of success.
By adopting Defactoâs STAR design solutions, major semiconductor companies are continuously moving from traditional and painful post synthesis design tasks up to RTL. The ROI for such a move has been proven for tens of projects.
For the devices we build today, design and implementation are unavoidably entangled. Design for low-power, test, reuse and optimized layout are no longer possible without taking implementation factors into account in design, and vice-versa. But design teams canât afford to iterate indefinitely between these phases, so they increasingly adapt design to implementation either by fiat (design components and architecture are constructed to serve a range of implementation needs and implementation must work within those constraints) or through restructuring where design hierarchy is adjusted in a bridging step to best meet the needs of power, test, layout and other factors.
Reaching power, performance and area (PPA) requirements for complex SoCs is becoming a real challenge. Restructuring an SoC design by building multiple variants of the same SoC with different PPA scenarios, is often needed. STAR provides a complete and powerful automation platform to restructure complex SoCs at both RTL or gate-level.
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